Commit Graph

58 Commits

Author SHA1 Message Date
Vas Crabb
76323eb770 srcclean and cleanup (nw) 2019-01-27 14:22:20 +11:00
tyfighter
9c3689f4dd MIPS3: Add minimal support for revealing the Secondary Cache Line size in the Status Register 2019-01-14 08:29:59 -06:00
MooglyGuy
b7cb1fc872 mips3: Fixed fastram accesses and COP0 exception handling. [Ryan Holtz] 2019-01-11 07:04:50 +01:00
mooglyguy
6ba8b0f1ae -mips, rsp: Removed MCFG, nw
-aleck64, hng64, kinst, namcops2, namcos23, ps2sony, pyson, vp101: Removed MACHINE_CONFIG_*, nw
2018-12-09 14:24:54 +01:00
mooglyguy
d2ed9eb110 mips3.cpp: Started laying the groundwork for cache support, nw 2018-11-19 06:15:34 +01:00
mooglyguy
7b4440920a -o2.cpp: Added CRIME and MACE skeleton devices. [Ryan Holtz]
-mips3.cpp: Various changes: [Ryan Holtz]
 * Added an #ifdef to display DPRINTF calls from the SGI O2 PROM.
 * Switched R4000BE/LE, R4400BE, R4600BE, and R5000BE to 64-bit data bus.
 * Fixed a bug that caused a crash with 64-bit data bus and the DRC.

-indy_indigo2.cpp: Moved a number of devices into HPC3. [Ryan Holtz]

-hpc3.cpp: Fixed an oversight with IRQs. [Ryan Holtz]
2018-11-18 21:51:53 +01:00
Patrick Mackinlay
9014ba4c17 mips3: add r4000 and r4400 variants (nw) 2018-09-19 20:07:43 +07:00
Ted Green
2ef5e202c0 Revert "MIPS3: Fixup LL/SC opcode operation. (nw)"
This reverts commit 326b1f7465.
2018-09-01 16:22:27 -06:00
Ted Green
326b1f7465 MIPS3: Fixup LL/SC opcode operation. (nw) 2018-09-01 15:44:54 -06:00
Vas Crabb
c0ab1c5aa4 (nw) srcclean and some cleanup:
* Make more #include guards follow standard format - using MAME_ as the prefix makes it easy to see which ones come from our code in a preprocessor dump, and having both src/devices/machine/foo.h and src/mame/machine/foo.h causes issues anyway
* Get #include "emu.h" out of headers - it should only be the first thing in a complilation unit or we get differences in behaviour with PCH on/off
* Add out-of-line destructors to some devices - it forces the compiler to instantiate the vtable in a certain location and avoids some non-deterministic compiler behaviours
2018-07-22 20:41:57 +10:00
smf-
28ab5679f2 You can't require a forward declared class (nw) 2018-07-21 11:18:35 +01:00
Robbbert
19ff23d2fd (nw) fixed the build. 2018-07-21 19:54:15 +10:00
mooglyguy
eed782f1e3 ps2sony: Some basic VU1 support, major file reshuffling, nw 2018-07-21 10:07:00 +02:00
mooglyguy
5db11a5e02 ps2sony: Checkpoint, nw 2018-07-17 18:14:24 +02:00
mooglyguy
cf34ccd3b4 ps2sony: Checkpoint. Adds a bunch of vector and parallel ops to the EE core, and skeleton GIF VIF1, and GS devices. 2018-07-14 04:00:29 +02:00
mooglyguy
f3ccd1f7f2 -ps2sony: Various DMA and SIF bug fixes, initial OSDSYS ELF transfers to IOP now, but EE and IOP hang immediately thereafter. nw 2018-07-05 19:04:50 +02:00
mooglyguy
eb5a8a3dc8 -ps2sony: Fleshing out the skeleton driver. [Ryan Holtz]
* Added ps2timer device to encapsulate Playstation 2 timers.
  * Temporarily hacked R5900 core to always have scratchpad RAM mapped at 0x70000000.
  * Added reference counting to divtlb so that it does not unmap pages that are still shared with other entries.
  * Added a considerable amount of logging to ps2sony.cpp.

-mips3: Added basic Emotion Engine support. [Ryan Holtz]
  * Added S bit to TLB mapping.

  * Added support for VSUB, VIADD, VSQI, VISWR, VOR, LQ, SQ, MFSA, MTSA, MFHI1, MFLO1, MULT1, DIV1, DIVU1, PEXTLW, PADDUW, PMFHI,
  PMFLO, PCPYLD, PCPYUD, SQC2, LQC2 opcodes. [Ryan Holtz]
2018-06-28 18:24:16 +02:00
Vas Crabb
90d7b40e62 srcclean and other cleanup (nw) 2018-06-24 19:04:53 +10:00
mooglyguy
b3d58bc431 mips3: Added VU0 macro-instructions to R5900 disassembler, pending split into separate device. nw 2018-06-23 19:56:02 +02:00
mooglyguy
dd30364632 mips3: Added disassembler for Emotion Engine core opcodes. VU macro ops are still to-do. [Ryan Holtz] 2018-06-23 12:59:38 +02:00
Olivier Galibert
4c24f25845 emumem: Rename direct_read_handler to memory_access_cache. Parametrize the template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert] 2018-05-11 18:23:04 +09:00
Vas Crabb
8142f24c43 don't pass so many naked pointers around (nw) 2018-03-25 01:44:45 +11:00
wilbertpol
3b923d59cc destaticify initializations (nw) (#3289)
* destaticify initializations (nw)

* fix this->set_screen (nw)
2018-03-04 04:18:08 +11:00
Olivier Galibert
c46e1007a8 emumem: API change [O. Galibert]
* direct_read_data is now a template which takes the address bus shift
  as a parameter.

* address_space::direct<shift>() is now a template method that takes
  the shift as a parameter and returns a pointer instead of a
  reference

* the address to give to {read|write}_* on address_space or
  direct_read_data is now the address one wants to access

Longer explanation:

Up until now, the {read|write}_* methods required the caller to give
the byte offset instead of the actual address.  That's the same on
byte-addressing CPUs, e.g. the ones everyone knows, but it's different
on the word/long/quad addressing ones (tms, sharc, etc...) or the
bit-addressing one (tms340x0).  Changing that required templatizing
the direct access interface on the bus addressing granularity,
historically called address bus shift.  Also, since everybody was
taking the address of the reference returned by direct(), and
structurally didn't have much choice in the matter, it got changed to
return a pointer directly.

Longest historical explanation:

In a cpu core, the hottest memory access, by far, is the opcode
fetching.  It's also an access with very good locality (doesn't move
much, tends to stay in the same rom/ram zone even when jumping around,
tends not to hit handlers), which makes efficient caching worthwhile
(as in, 30-50% faster core iirc on something like the 6502, but that
was 20 years ago and a number of things changed since then).  In fact,
opcode fetching was, in the distant past, just an array lookup indexed
by pc on an offset pointer, which was updated on branches.  It didn't
stay that way because more elaborate access is often needed (handlers,
banking with instructions crossing a bank...) but it still ends up with
a frontend of "if the address is still in the current range read from
pointer+address otherwise do the slowpath", e.g. two usually correctly
predicted branches plus the read most of the time.

Then the >8 bits cpus arrived.  That was ok, it just required to do
the add to a u8 *, then convert to a u16/u32 * and do the read.  At
the asm level, it was all identical except for the final read, and
read_byte/word/long being separate there was no test (and associated
overhead) added in the path.

Then the word-addressing CPUs arrived with, iirc, the tms cpus used in
atari games.  They require, to read from the pointer, to shift the
address, either explicitely, or implicitely through indexing a u16 *.
There were three possibilities:

1- create a new read_* method for each size and granularity.  That
   amounts to a lot of copy/paste in the end, and functions with
   identical prototypes so the compiler can't detect you're using the
   wrong one.

2- put a variable shift in the read path.  That was too expensive
   especially since the most critical cpus are byte-addressing (68000 at
   the time was the key).  Having bit-adressing cpus which means the
   shift can either be right or left depending on the variable makes
   things even worse.

3- require the caller to do the shift himself when needed.

The last solution was chosen, and starting that day the address was a
byte offset and not the real address.  Which is, actually, quite
surprising when writing a new cpu core or, worse, when using the
read/write methods from the driver code.

But since then, C++ happened.  And, in particular, templates with
non-type parameters.  Suddendly, solution 1 can be done without the
copy/paste and with different types allowing to detect (at runtime,
but systematically and at startup) if you got it wrong, while still
generating optimal code.  So it was time to switch to that solution
and makes the address parameter sane again.  Especially since it makes
mucking in the rest of the memory subsystem code a lot more
understandable.
2017-11-29 10:32:31 +01:00
Olivier Galibert
6caef2579a dvdisasm: Overhaul [O. Galibert]
Disassemblers are now independant classes.  Not only the code is
cleaner, but unidasm has access to all the cpu cores again.  The
interface to the disassembly method has changed from byte buffers to
objects that give a result to read methods.  This also adds support
for lfsr and/or paged PCs.
2017-11-26 17:41:27 +01:00
Vas Crabb
1e8c0b23c3 This is too contentious, please put it up for review
Revert "Changes to debugger memory address translation"

This reverts commit bb0964f9a2.
2017-08-01 15:19:44 +10:00
AJR
bb0964f9a2 Changes to debugger memory address translation
- memory_translate now returns an address space number rather a boolean flag, permitting addresses in part of one space to map to an entirely different space. This is primarily intended to help MCUs which have blocks of internal memory that can be dynamically remapped, but may also allow for more accurate emulation of MMUs that drive multiple external address spaces, since the old limit of four address spaces per MAME device has been lifted.
- memory_translate has also been made a const method, in spite of a couple of badly behaved CPU cores that can't honestly treat it as one.
- The (read|write)_(byte|word|dword|qword|memory|opcode) accessors have been transferred from debugger_cpu to device_memory_interface, with somewhat modified arguments corresponding to the translate function it calls through to if requested.
2017-08-01 00:21:19 -04:00
Vas Crabb
536b2153d9 make device_memory_interface slightly less of a special case, use a typedef to avoid nested templates everywhere (nw) 2017-07-10 19:35:07 +10:00
Olivier Galibert
cbbbd07484 dimemory: Lift the cap on the number of address spaces per device [O. Galibert] 2017-07-03 08:03:57 +02:00
smf-
e141a1c3b7 more incorrect names fixed (nw) 2017-05-14 21:17:21 +01:00
Vas Crabb
0f0d39ef81 Move static data out of devices into the device types. This is a significant change, so please pay attention.
The core changes are:
* Short name, full name and source file are no longer members of device_t, they are part of the device type
* MACHINE_COFIG_START no longer needs a driver class
* MACHINE_CONFIG_DERIVED_CLASS is no longer necessary
* Specify the state class you want in the GAME/COMP/CONS line
* The compiler will work out the base class where the driver init member is declared
* There is one static device type object per driver rather than one per machine configuration

Use DECLARE_DEVICE_TYPE or DECLARE_DEVICE_TYPE_NS to declare device type.
* DECLARE_DEVICE_TYPE forward-declares teh device type and class, and declares extern object finders.
* DECLARE_DEVICE_TYPE_NS is for devices classes in namespaces - it doesn't forward-declare the device type.

Use  DEFINE_DEVICE_TYPE or DEFINE_DEVICE_TYPE_NS to define device types.
* These macros declare storage for the static data, and instantiate the device type and device finder templates.

The rest of the changes are mostly just moving stuff out of headers that shouldn't be there, renaming stuff for consistency, and scoping stuff down where appropriate.

Things I've actually messed with substantially:
* More descriptive names for a lot of devices
* Untangled the fantasy sound from the driver state, which necessitates breaking up sound/flip writes
* Changed DECO BSMT2000 ready callback into a device delegate
* Untangled Microprose 3D noise from driver state
* Used object finders for CoCo multipak, KC85 D002, and Irem sound subdevices
* Started to get TI-99 stuff out of the TI-990 directory and arrange bus devices properly
* Started to break out common parts of Samsung ARM SoC devices
* Turned some of FM, SID, SCSP DSP, EPIC12 and Voodoo cores into something resmbling C++
* Tried to make Z180 table allocation/setup a bit safer
* Converted generic keyboard/terminal to not use WRITE8 - space/offset aren't relevant
* Dynamically allocate generic terminal buffer so derived devices (e.g. teleprinter) can specify size
* Imporved encapsulation of Z80DART channels
* Refactored the SPC7110 bit table generator loop to make it more readable
* Added wrappers for SNES PPU operations so members can be made protected
* Factored out some boilerplate for YM chips with PSG
* toaplan2 gfx
* stic/intv resolution
* Video System video
* Out Run/Y-board sprite alignment
* GIC video hookup
* Amstrad CPC ROM box members
* IQ151 ROM cart region
* MSX cart IRQ callback resolution time
* SMS passthrough control devices starting subslots

I've smoke-tested several drivers, but I've probably missed something.  Things I've missed will likely blow up spectacularly with failure to bind errors and the like.  Let me know if there's more subtle breakage (could have happened in FM or Voodoo).

And can everyone please, please try to keep stuff clean.  In particular, please stop polluting the global namespace.  Keep things out of headers that don't need to be there, and use things that can be scoped down rather than macros.
It feels like an uphill battle trying to get this stuff under control while more of it's added.
2017-05-14 21:44:11 +10:00
arbee
8ce5aa566f MIPS: initial support for VR5500 and TX4925 CPUs. [R. Belmont] 2017-03-25 17:08:21 -04:00
Happy
247a889090 mips3: Retry fixing FPU register aliasing 2017-02-26 20:21:17 -07:00
Vas Crabb
7238415d1f srcclean (nw) 2016-11-27 09:56:49 +11:00
Nathan Woods
c65cdadcbf Changing the MIPS DRC to not use static char buffers when disassembling 2016-11-20 10:18:13 -05:00
Nathan Woods
a29891d2e5 Changed disassembler infrastructure to not use char buffers internally 2016-11-20 08:49:30 -05:00
Nathan Woods
c68d5ad9bf Put the declaration of dasmmips3() in a header file 2016-11-16 07:33:32 -05:00
Miodrag Milanovic
1446bd7ecd converted lot of TRUE/FALSE to real boolean and updated types (nw) 2016-10-22 17:35:04 +02:00
Miodrag Milanovic
ddb290d5f6 NOTICE (TYPE NAME CONSOLIDATION)
Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8
also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
2016-10-22 13:13:17 +02:00
smf-
a67bcb06ff fix disassembly window (nw) 2016-10-18 15:17:25 +01:00
therealmogminer@gmail.com
0b544df0c2 Port Happy's PPC aliasing fix to the MIPS3 DRC, nw 2016-04-15 05:00:15 +02:00
AJR
0d8df9d595 Make generic VTLB implementation a modern device interface (nw) 2016-02-07 01:42:58 -05:00
Miodrag Milanovic
4e8e3066f8 reverting:
SHA-1: 1f90ceab07

* tags are now strings (nw)
fix start project for custom builds in Visual Studio (nw)
2016-01-20 21:42:13 +01:00
Miodrag Milanovic
7c9cd3feea Revert "rest of device parameters to std::string (nw)"
This reverts commit caba131d84.
2016-01-20 21:35:11 +01:00
Miodrag Milanovic
caba131d84 rest of device parameters to std::string (nw) 2016-01-16 20:05:32 +01:00
Miodrag Milanovic
1f90ceab07 tags are now strings (nw)
fix start project for custom builds in Visual Studio (nw)
2016-01-16 14:54:42 +01:00
Miodrag Milanovic
603dfb67c4 Revert "remove const (nw)"
This reverts commit e96fd34dd8.
2016-01-13 13:29:06 +01:00
Miodrag Milanovic
e96fd34dd8 remove const (nw) 2016-01-11 09:58:36 +01:00
AJR
115db95642 Return std::string objects by value rather than pass by reference
- strprintf is unaltered, but strformat now takes one fewer argument
- state_string_export still fills a buffer, but has been made const
- get_default_card_software now takes no arguments but returns a string
2016-01-10 16:36:18 -05:00
Miodrag Milanovic
a55ab6d615 some handmade changes (nw) 2015-12-21 16:01:14 +01:00