* start looking at the extra opcodes in the SSD 2000 type XaviX chip (seems some undocumented 6502 opcodes are replaced with more custom ones)
* (nw)
* the xavix memory mapping gets stranger with each piece of new evidence (nw)
* Move around the debugger hooks to get a small but measurable performance increase
* Remove emucore from external tools
* Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* create derived 6502 type for XaviX because it has at least one custom 4-byte opcode that doesn't fit any other type.
treating that opcode as NOP for now.
have a feeling it might be something to do with the other integrated hardware, might be 'execute co-processor code chain at this address' or something similar
It isn't a standard JSL (Jump Subroutine Long) like the SNES cpu opcode in the same place as this, it seems to point at some code-like structures tho)
could also be a secondary operation mode with different encoding like ARM's Thumb mode tho I guess.
We currently only have a single XaviX based dump (taitons1) but there are more on the way. I'm going to see if the code flow makes any sense at all with these missing, or if any of it gives a clue as to what they should actually do.
* xavix - let's call these callf and retf then
after further investigation these are some kind of extra 'long jump' subroutine / task handlers, the 0x80 also being a custom opcode was throwing me off trying to identify them before.
looks like they might have been hacking 65816 features into the regular 6502 core?
* prepare for extra address bits (nw)
* better program flow (nw)
- Separate disassembler for i802x (including unemulated 8022 instructions)
- Provide separate (though mostly just more limited) 8021 opcode table
- Writes to 8021 P0 no longer go through memory space
please people, remember to keep source UTF-8 and if you're committing on behalf of others, clean up indents to meet MAME conventions
anyone can run srcclean over a submission and see what will get hit
Disassemblers are now independant classes. Not only the code is
cleaner, but unidasm has access to all the cpu cores again. The
interface to the disassembly method has changed from byte buffers to
objects that give a result to read methods. This also adds support
for lfsr and/or paged PCs.
What works:
* HP85A machine with 16K of RAM
* Capricorn CPU works
* Keyboard works (with minor issues)
* CRT text / graphics modes work (correct speed is not emulated yet so service ROM complaints)
* BASIC is usable
What is missing (and I'll have hopefully working soon):
* HW timers
* Beeper
* Integral printer
* DC100 cassette drive
* Extension ROMs
* I/O modules (especially the HPIB interface so that we can hook up floppy drives)
* Other models in the family (e.g. HP86)
* Renamed to MCS-40.
* Emulated 8-clock instruction cycle, interruptible at any point.
* Converted TEST input to an input line.
* Added SYNC and CM output lines.
* Added support for 4040 CY output, logical operations, extended registers, ROM banking and disassembly.
* Made I/O space mapping more flexible to support the variety of peripherals available.
* Notable missing features are 4040 interrupt and halt, and "program memory" space.
* Added m146805 and m68hc05 to unidasm
* Made opcode tables configurable in m6805_base_device, provided tables for HMOS, CMOS and HC families
* Implemented MUL instruction, made unimplemented STOP and WAIT raise fatal error
* Added skeleton MC68HC05C4 with RAM and ROM in correct locations in memory map
Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8
also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* Note that this omits non-VIS OSA 2007/2011 features
* VIS 2+ ldtxa/ldtwa/sttwa still uses ldda/stda, using new mnemonics requires special-casing this instruction and checking ASI
