Commit Graph

1132 Commits

Author SHA1 Message Date
Miodrag Milanovic
d198a773e6 Fixed assert in z80 cpu core when using nsc800 (no whatsnew) 2010-05-25 06:57:29 +00:00
Fabio Priuli
0fb8703972 Added NSC800 CPU emulation to the Z80 core [Sandro Ronco] 2010-05-25 05:33:13 +00:00
Michaël Banaan Ananas
6a325434b0 rm logerror flood 2010-05-23 19:10:13 +00:00
Michaël Banaan Ananas
ae91cd0d17 - even more small company name cleanups
- "Somecompany License -> "Somecompany license" (no caps)
- corrected "licence" typos, there were lots
2010-05-22 20:51:23 +00:00
Couriersud
b6d4643281 Improved Z180 interrupt and timer handling. Added some missing save state entries and fixed HALT. [Couriersud] 2010-05-20 21:50:00 +00:00
Couriersud
fcf1a326f5 Rewrote Z180 cycle accounting to create a basis for more exact internal I/O and timer operations as well as implementing interrupt priorities. Removed unused BIG_SWITCH code as well. [Couriersud] 2010-05-19 18:00:06 +00:00
Couriersud
8deddc4cf6 Improved Z180 timer and HALT processing. This fixes MT03852. [Couriersud] 2010-05-17 21:45:17 +00:00
Scott Stone
79a40737bd Remove all references to the nonexistent "premov" instruction from the NEC-V core. [Alex Jackson] 2010-05-15 20:57:15 +00:00
Couriersud
0c62bdc768 S2650_SENSE_PORT is now active when data written is != 0 and inactive when data == 0. It now acts as a line in a mame-sense. [Couriersud] 2010-05-13 10:46:31 +00:00
Angelo Salese
ed087d2be6 Duh 2010-05-12 02:26:00 +00:00
Angelo Salese
1e0f3da2e0 Fix debug compile? 2010-05-12 02:14:00 +00:00
Angelo Salese
460e4e92d8 More z8001 work 2010-05-12 00:33:51 +00:00
Angelo Salese
14606da3b8 First batch of Zilog Z8001 mods (treated as a separate CPU core for now) 2010-05-11 23:50:29 +00:00
Angelo Salese
3f3cf7748d Placeholder for the Zilog Z8001 CPU core 2010-05-11 20:38:31 +00:00
Michaël Banaan Ananas
f088a2539c tafoid yes, surely a copypaste error 2010-05-05 21:45:09 +00:00
Scott Stone
b26dcde9d3 Fixed 03830: All sets in harddriv.c: Message: Duplicate save state registration entry (DSP32C/dsp32/0/cpustate->pin) 2010-05-05 18:22:53 +00:00
Fabio Priuli
42e9ddf60d added save states to the following CPU: apexc, asap, avr8, cp1610, dsp32 and f8 [Fabio Priuli] 2010-04-27 09:09:41 +00:00
Scott Stone
cb93774e22 Disable many unused variables as identifed by cppcheck. [Oliver Stöneberg] 2010-04-23 23:21:39 +00:00
Phil Bennett
3b13698e25 i386dasm.c: Corrected display of debug registers (D0-D7) in disassembly listings [Barry Rodewald] 2010-04-17 18:22:22 +00:00
Curt Coder
811b900a21 F8 cpu disassembler improvements [Curt Coder]:
- fixed branch target PC
- added BP,BC,BZ,BR,BM,BNC,BNZ,BNO mnemonics
- removed extraneous $ from 2 byte hex values
2010-04-17 15:11:53 +00:00
Wilbert Pol
5221944315 sm8500d.c: Fixed disassembly of extended instructions (1A, 1B, 4F). [Oliver Stoeneberg]
lr35902.c: Fixed possible issue when checking for enabled irqs.  [Oliver Stoeneberg]
2010-04-10 18:02:28 +00:00
Angelo Salese
85283ac532 Fixed RTL opcode in-bank issue in the G65816 CPU core [Angelo Salese] 2010-04-10 15:50:08 +00:00
Aaron Giles
1390af8fa4 Cleanups and version bump. 2010-04-08 06:14:23 +00:00
Angelo Salese
13c095c03c First step in supporting master cycle delays in the SNES driver [Angelo Salese] 2010-04-06 23:04:22 +00:00
Wilbert Pol
39ba484e7b uPD7801: Fixed the MOV MC,A instruction. 2010-04-05 18:53:22 +00:00
Angelo Salese
5da4dfa346 Added boundary checks for MVN and MVP opcodes when in M mode in the G65816 CPU core [Angelo Salese] 2010-04-04 14:41:35 +00:00
Ryan Holtz
ceccc811e5 Disabled DRC versions of certain vector load/store operations in the
RSP core in order to avoid geometry issues. [Harmony]
2010-04-03 21:03:20 +00:00
Miodrag Milanovic
983b3e482a [8080/8085 CPU] Fix of mametester bug 3227. [Robbbert] 2010-04-03 12:30:52 +00:00
Phil Bennett
e8914bb8c2 i386/NEC disassembler updates: [Alex Jackson]
* Made "MOV AL, offset" etc (opcodes A0-A3) properly indicate a segment override prefix.
 * Corrected the disassembly of various NEC-only instructions (mainly V25/V35-only instructions)
 * Changed CPUINFO_INT_MAX_INSTRUCTION_BYTES on i86 and NEC from 15 to 8.
2010-04-01 11:38:01 +00:00
Phil Bennett
3354dc342b i386+ core updates: [Samuele Zannoli]
* Added CR4 register
 * Added bswap instruction
 * Added support for 4MB pages
2010-03-31 21:25:15 +00:00
Fabio Priuli
32066d6cd7 snes.c wip: fixed reserved memory address read not returning open_bus; fixed a few add-on chip reads not returning open_bus [Fabio Priuli]
side-note: CX4_read should return open_bus as well in a few cases, but passing an address_space to the handler would require more changes than are worth right now (especially because no game needs it). It will be taken care of when I convert all add-on chip handlers to become read/write handlers...
2010-03-30 08:11:56 +00:00
Fabio Priuli
3ebf3a2e92 superfx.c: added save states to the CPU [Fabio Priuli]
snes.c: moved some more variables to driver state, set a few addresses as open bus and slightly changed SuperFX handlers not to access SNES WRAM [Fabio Priuli]
2010-03-29 11:13:53 +00:00
R. Belmont
9d08284569 m680x0 FPU updates: [R. Belmont]
- BCD packed decimal now supported, including k-factor
- Improved FSAVE/FRESTORE including FPU reset when restoring a NULL frame
- FREM instruction supported
- Better disassembly of FPU instructions
2010-03-29 02:50:17 +00:00
Aaron Giles
a91446eaca Cleanups and version bump. 2010-03-25 13:18:38 +00:00
Angelo Salese
905c826a97 MC68HC11: Implemented SUBD DIR & SUBD EXT opcodes [Angelo Salese] 2010-03-24 13:27:07 +00:00
Angelo Salese
70e0a16942 Small printf bugfix 2010-03-24 12:06:35 +00:00
R. Belmont
80637b51a4 MN10200 updates: [R. Belmont]
- Better IRQ generation and hookup to MAME IRQ system
- Preliminary 8-bit timer hookup including prescalers and IRQs
- Fixed issue with debugger not showing registers correctly
2010-03-22 01:05:32 +00:00
Fabio Priuli
4118089801 Fixed VS2010 compiling 2010-03-18 07:33:29 +00:00
Angelo Salese
c1a7ef2ef5 Added default nvram to Cyber Commando, and improved the default control mapping in it [David Haywood] 2010-03-17 19:26:25 +00:00
Fabio Priuli
c02b195ede several cleanups based on cppcheck and VS2008 Code Analysis [Oliver Stöneberg]
split.c: made the "split" return the actual result instead of just 0. [Oliver Stöneberg]

clifront.c: made the identation of the CPU device in -listdevices the same like the others [Oliver Stöneberg]

i386.c: gave some fatalerror() calls in the i386 proper messages [Oliver Stöneberg]

ssem.c: fixed compilation of SSEM core with SSEM_DISASM_ON_UNIMPL [Oliver Stöneberg]

srcclean.c: small wording change in the srcclean summary [Oliver Stöneberg]

sdl/window.c: fixed a potential memory leak in  sdlwindow_video_window_create() [Oliver Stöneberg]
2010-03-17 11:59:16 +00:00
Fabio Priuli
585c85dbae i386: fixed unaligned memory accesses and opcode fetches
when they cross a page boundary. Previously, if pages
were not ordered in contiguous RAM, then a cross-boundary 
read or write would read partially incorrect data or write 
some of the data in the wrong page. [Barry Rodewald]
2010-03-17 09:56:42 +00:00
Fabio Priuli
47a1fe17f8 spc700.c: Added save states [Fabio Priuli]
snes.c: Updated the snes sound device to use device handlers, to store its internals in a struct, and to save them [Fabio Priuli]
2010-03-17 09:33:15 +00:00
Fabio Priuli
9aa86db4c8 tlcs90.c: added save states [Fabio Priuli]
ddenlovr.c, dynax.c: replaced memory_set_bankptr with memory_set_bankp and added save state support [Fabio Priuli]


side note: this and rev.8619 took definitely more time than I expected (especially to test as many drivers as possible), but there should be no regressions
/me crossing fingers
2010-03-17 08:22:06 +00:00
R. Belmont
db51ba1803 680x0 FPU update: [R. Belmont]
- Implemented FMOVECR
- Added load extended PC relative indexed support
- Cleanup some duplicated code
2010-03-14 21:13:32 +00:00
R. Belmont
707f597134 65816: fix decimal mode ADC/SBC behavior [blargg, byuu, R. Belmont] 2010-03-14 00:53:08 +00:00
R. Belmont
baf6a9cd0b 680x0 FPU updates [R. Belmont]
- Rewritten to use SoftFloat instead of unportable native FP math
- Support added for Motorola 96-bit extended floats
- More addressing modes and conditions supported


The taitojc games function identically to the old implementation (I stepped 
through the main matrix multiply in dendeg and the registers never diverged) 
and speed on Core 2 Duo is a wash - sometimes softfloat's faster, sometimes 
not, but the difference on -str 90 never exceeded 1%.
2010-03-12 05:41:10 +00:00
Aaron Giles
db163391eb Cleanups and version bump. 2010-03-11 07:08:54 +00:00
Ryan Holtz
5d5ec72024 Slightly fixed interrupt handling and added SBIC and MUL opcodes to the Atmel AVR8 core. [Harmony]
Added FJMP/JMPF opcode to the SunPlus u'nSP core. [Segher, Harmony]

Performed an initial code cleanup pass on the N64 rendering code to make use of booleans and inline variable instantiation, and removed a number of unused variables that were exposed as a result of the latter. [Harmony]
2010-03-11 06:49:53 +00:00
R. Belmont
4c0a6f40e7 680x0: Improve disassembly for various FMOVE forms [R. Belmont] 2010-03-11 05:23:24 +00:00
R. Belmont
dfff696a55 [#03533] Properly show 32-bit displacement for 020+ A reg relative [R. Belmont] 2010-03-11 04:50:27 +00:00