I've added a new device type and bare bones loading of them so you can see the code running however the communication with the main CPU is not hooked up yet so they still fallback to the simulation code.
also made nbamht a parent, because the nbamht / nbahangt situation really isn't too different to the umk3 / mk3 or sf2ce / sf2 situations, it's a distinct new release.
hooked up new 68705 dump to Tokio / Scramble Formation [David Haywood]
New Working Games
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Tokio / Scramble Formation [ShouTime, brizzo, David Haywood]
as this is a lengthy task I've created a derived CPU type with the new functionality to aid in the process without disrupting existing drivers that haven't yet been updated.
started with tiger heli / slap fight.
atlantis: Renamed uart ports. (nw)
iteagle: Remapped service buttons to standard location.
iteagle: Connected cdrom and started adding rs232 communication ports. (nw)
- Allow stringing multiple callbacks together recursively. Chained callbacks will be read or written in sequence, and each can be configured with its own type and mask/shift/XOR parameters.
- Chained input callbacks cannot have overlapping masks (there's no such thing as a free multiplex). Chained output callbacks have no such restriction.
- Remove the constant parameter for the LOGGER callback type: it makes no sense for output, was always zero in existing usage, and is now unnecessary with callback chaining.
- Change LOGGER behavior for writes to log the user-defined message only if the output as masked is nonzero. With callback chaining, this can be used to monitor when individual bits become active.
- Constant read callbacks can no longer have MCFG_DEVCB_XOR or MCFG_DEVCB_INVERT specified (makes no sense in this context).
- Add a MEMBANK callback type to allow output bits to be used for bank-switching.
- Add ASSERTLINE and CLEARLINE callback types that raise or lower an interrupt line if the selected bit of the written value is active. These are intended for where periodic or ready-pulse signals from devices are used to trigger IRQs that the CPU program will independently acknowledge.
- Add MCFG_DEVCB_BIT as shorthand for masking and shifting out an individual bit for a callback.
- Removed DEVCB_LINE_DISPATCH_<n>. Where we're going, we don't need line dispatcher devices.
The incompatibility of compilers with regard to post-C90 printf string formats is shockingly bad. There seems to be no easy way to format a 64-bit value and please both gcc and clang, let alone MSVC.
* 7473: Made device only transition on a falling clock.
* 74161: Inverted Clear and Clock inputs to match datasheet.
* 74260: Fixed number of inputs.
* Am2847: Fixed shift register size (was 160 bits, should have been 80 bits)
* DM9334: Inverted C and E inputs to match datasheet.
-netlist: Added new devices: [Ryan Holtz]
* Intel 2102A 1Kbit (1024 x 1) Static RAM
* 74365 Hex Bus Driver with 3-State Outputs
* Generic 2- and 3-terminal Tristate device
* Note: Tristate device and 74365 do not actually tristate, they are simply a way of combining multiple outputs + chip enables.
alignment exceptions will need more complex mask/shit depending on the instruction's addressing mode, but that's a job for another time; at any rate it uses the LSBs of the DSISR register (nw)
